Datasheet

Advance Information MC68HC908GP20 — Rev 2.1
126 Freescale Semiconductor
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF always
reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control
register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Address: $0036
Bit 7654321Bit 0
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)