Datasheet

Analog Integrated Circuit Device Data
42 Freescale Semiconductor
07XSC200
5.4.4.1 Previous Address SOA4 : SOA0 = 1A000 (STATR_s)
The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (V
SUPPLY(POR)
). This bit is only reset by
a read operation.
Bits OD7: OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits
SOA3 = A
(Table 22).
OC_s: overcurrent fault detection for a selected output,
SC_s: severe short-circuit fault detection for a selected output,
OS_s: output shorted to VPWR fault detection for a selected output,
OLOFF_s: OpenLoad in OFF state fault detection for a selected output,
Table 22. Serial Output Bit Map Description
Previous
STATR
SO Returned Data
S
O
A
4
S
O
A
3
S
O
A
2
S
O
A
1
S
O
A
0
OD
15
OD
14
OD
13
OD
12
OD
11
OD
10
O
D9
OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
STATR
_s
1 A 0 0 0
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
POR UV OV
OLON
_s
OLOF
F_s
OS_s OT_s SC_s OC_s
PWMR
_s
1 A 0 0 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
28W
_s
ON_
s
PWM
6_s
PWM
5_s
PWM
4_s
PWM3_s PWM2_s PWM1_s PWM0_s
CONF
R0_s
1 A 0 1 0
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
X X X
DIR_d
is_s
SR1_
s
SR0_s DELAY2_s DELAY1
_s
DELAY0
_s
CONF
R1_s
1 A 0 1 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
X X
Retry_
unlimit
ed_s
Retry_
dis_s
OS_di
s_s
OLON_dis
_s
OLOFF_dis
_s
OLLED_
en_s
CSNS_r
atio_s
OCR_s 1 A 1 0 0
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
Xeno
n_s
BC1
_s
BC0_
s
OC1_
s
OC0_
s
OCHI_s OCLO1_s OCLO0_
s
OC_mod
e_s
GCR 0 0 1 0 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
VDD
_FAI
L_e
n
PW
M_e
n
CLOC
K_sel
TEMP
_en
CSNS
_en
CSNS1 CSNS0 X OV_dis
DIAGR
0
0 0 1 1 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
X X X X X
X CLOCK_fail
CAL_fail OTW
DIAGR
1
0 1 1 1 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
X X X X IN1
IN0 X
X WD_en
DIAGR
2
1 0 1 1 1
WDI
N
SO
A4
SOA
3
SOA
2
SO
A1
SO
A0
N
M
X X X X X
X0
1 0
Regist
er
state
after
RST
=
0 or
V
DD(F
AIL)
or
V
SUPP
LY(POR
)
conditi
on
N/
A
N/
A
N/
A
N/
A
N/
A
0 0 0 0 0 0 0 X 0 0 0 0
00
0 0
s = Output selection with the bit A
as defined in Table 11