Datasheet

Analog Integrated Circuit Device Data
40 Freescale Semiconductor
07XSC200
Figure 15. Overcurrent Profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17.
Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18.
Address 00101 — GLObal configuration regIster (GCR)
The GCR register allows the MCU to configure the device through the SPI.
Bit D8 allows the MCU to enable or disable the V
DD
failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs
HS[0:1] with PWMR register device in Fail-safe mode in case of V
DD
< V
DD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:1]
with PWMR register (the direct input states are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19.
Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20.
Table 17. Output Steady State Selection
OCLO1 (D2) OCLO0 (D1) Steady State Current
0 0 OCLO2 (default)
01 OCLO3
10 OCLO4
11 OCLO1
Table 18. Overcurrent Mode Selection
OC_mode_s (D0) Overcurrent Mode
0 only inrush current management (default)
1 inrush current and bulb cooling
management
Table 19. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6) PWM module
0 X PWM module disabled (default)
1 0 PWM module enabled with external
clock from CLOCK
1 1 PWM module enabled with
internal calibrated clock
I
OCH1
I
OCH2
I
OC1
I
OC2
I
OC3
I
OC4
I
OCL3
I
OCL2
I
OCL1
t
OC1
t
OC2
t
OC3
t
OC4
t
OC5
t
OC6
t
OC7
Time
I
OCL4