Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 37
07XSC200
5.4.2 Device Register Addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
5.4.2.1 Address XX000 — Status Register (STATR_s)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to
the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR
and CALR registers (Refer to
Serial Output Communication (Device Status Return Data).
5.4.2.2 Address A
1
A
0
001— Output PWM Control Register (PWMR_s)
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state of the D13 bit (Table 11).
A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2, and the
inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs.
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also
pulled down). Bits D6:D0 set the output PWM duty cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 6.
5.4.2.3 Address A
1
A
0
010— Output Configuration Register (CONFR0_S)
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14
: D13 bits (Table 11).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable
the output from direct control (in this case, the output is only controlled by the On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default
value [00] corresponds to the medium speed slew rate (Table 12).
Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as
shown
Table 7, (only available for PWM_en bit is set to logic [1]).
5.4.2.4 Address A
1
A
0
011 — Output Configuration Register (CONFR1_s)
The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s”
is independently selected for configuration based on the state of the D14
: D13 bits (Table 11).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the auto-retry counter for the selected output, the default value [0]
corresponds to enable auto-retry feature with time limitation.
Table 11. Output Selection
A (D13) HS Selection
0 HS0 (default)
1HS1
Table 12. Slew Rate Speed Selection
SR1_s (D4) SR0_s (D3) Slew Rate Speed
0 0 medium (default)
01low
1 0 high
11Not used