Datasheet

Analog Integrated Circuit Device Data
30 Freescale Semiconductor
07XSC200
During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default
value (except POR bit) and fault protections are fully operational.
The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
5.2.4 Normal & Fail-safe Mode Transitions
Transition Fail-safe to Normal mode
To leave the Fail-safe mode, V
DD
must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit
set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (auto-
retry included).
Moreover, the device can be brought out of the Fail-safe mode due to watchdog time-out issue by forcing the FSI pin to logic [0].
Transition Normal to Fail-safe mode
To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into
Fail-safe mode (auto-retry included).
5.2.5 Fault Mode
The 07XSC200 is in Fault mode when:
•V
PWR
and V
DD
are within the normal voltage range,
• wake-up = 1,
• fail = X,
•fault=1.
This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:
• Overtemperature fault,
• Overcurrent fault,
• Severe short-circuit fault,
• Output(s) shorted to V
PWR
fault in OFF state,
• OpenLoad fault in OFF state,
• Overvoltage fault (enabled by default),
• Undervoltage fault.
The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI
communication.
The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x])
and the FS pin.
5.2.6 Start-up Sequence
The 07XSC200 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to normal mode with SPI register content is
reset (as defined in Table 10 and Table 22). All features of the 07XSC200 will be available after 50 s typical, and all SPI
registers are set to default values (set to logic [0]).
• toggle WD bit from 0 to 1.
And, in case the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
Table 8. SPI Watchdog Activation
Typical RFSI () Watchdog
0 (shorted to ground) Disabled
(open) Enable