Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 29
07XSC200
The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a
specified frequency range (from f
CLOCK(LOW)
to f
CLOCK(HIGH)
). In case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
5.2.2.2 Calibratable Internal Clock
The internal clock can vary as much as 30 percent corresponding to typical f
PWM(0)
output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 07XSC200 allows clock period
setting within 10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration
pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin
transitions from logic [1] to [0] until from logic [0] to [1] determines the period of internal clock with a multiplicative factor of 128.
In case a negative CSB pulse is outside a predefined time range (from t
CSB(MIN)
to t
CSB(MAX)
), the calibration event will be ignored
and the internal clock will be unaltered or reset to the default value (f
PWM(0)
), if this was not calibrated before.
The calibratable clock is used, instead of the clock from CLOCK input, when CLOCK_sel is set to [1].
5.2.3 Fail-safe Mode
The 07XSC200 is in Fail-safe mode when:
•V
PWR
is within the normal voltage range,
• wake-up = 1,
• fail = 1,
•fault = 0.
5.2.3.1 Watchdog
If the FSI input is not grounded, the watchdog time-out detection is active when either the WAKE or IN_ON[0:1] or RSTB input
pin transitions from logic
[0] to logic [1]. The WAKE input is capable of being pulled up to V
PWR
with a series of limiting resistance
limiting the internal clamp current according to the specification.
The watchdog time-out is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog time-out period (WDTO), the device will operate normally.
5.2.3.2 Fail-safe Conditions
If an internal watchdog time-out occurs before the WD bit for FSI open (Table 8) or in case of V
DD
failure condition (V
DD
<
V
DD(FAIL)
)) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1]
(see fail-safe to normal mode transition paragraph) and V
DD
is within the normal voltage range.
CS
SI
CALR
SI command
ignored
Internal
clock duration