Datasheet

Analog Integrated Circuit Device Data
28 Freescale Semiconductor
07XSC200
To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal mode with RSTB pin set to
logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0 V on the VDD
supply pin to switch the device to Sleep state.
5.2.2 Normal Mode
The 07XSC200 is in Normal mode when:
•V
PWR
and V
DD
are within the normal voltage range,
• wake-up = 1,
• fail = 0,
•fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:1] are under control, as defined by the hson signal:
hson[x] = (((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:
fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).
5.2.2.1 Programmable PWM Module
The outputs HS[0:1] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from CLOCK input pin or from the internal clock is the factor 2
7
(128) of the output PWM frequency
(CLOCK_sel bit). The outputs HS[0:1] can be controlled in the range of 5.0 to 98% with a resolution of 7 bits of duty cycle
(Table 6). The state of other IN pin is ignored.
The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC
behavior of the light module (Table 7).
Table 6. Output PWM Resolution
On bit Duty cycle Output state
0 X OFF
1 0000000 PWM (1/128 duty cycle)
1 0000001 PWM (2/128 duty cycle)
1 0000010 PWM (3/128 duty cycle)
1 n PWM ((n+1)/128 duty cycle)
1 1111111 fully ON
Table 7. Output PWM Switching Delay
Delay bits Output delay
000 no delay
001 16 PWM clock periods
010 32 PWM clock periods
011 48 PWM clock periods
100 64 PWM clock periods
101 80 PWM clock periods
110 96 PWM clock periods
111 112 PWM clock periods