Datasheet

Analog Integrated Circuit Device Data
42 Freescale Semiconductor
10XSC425
6.4.2 Device Register Addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
6.4.2.1 Address XX000 — Status Register (STATR_s)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to
the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR
and CALR registers (Refer to the section entitled
Serial Output Communication (Device Status Return Data).
6.4.2.2 Address A
1
A
0
001— Output PWM Control Register (PWMR_s)
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is
independently selected for configuration, based on the state of the D14 : D13 bits (Table 12).
A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2 and, the
inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs. This bit it not taken into account for HS[2,3]
outputs.
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also
pulled down). Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown
Table 7.
6.4.2.3 Address A
1
A
0
010— Output Configuration Register (CONFR0_S)
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14 : D13 bits (Table 12).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable
the output from direct control (in this case, the output is only controlled by the On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high, medium, or low speed slew rate for the selected output, the default
value [00] corresponds to the medium speed slew rate (
Table 13).
Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as
shown Table 8 (only available for PWM_en bit is set to logic [1]).
Table 12. Output Selection
A
1
(D14) A
0
(D13) HS Selection
0 0 HS0 (default)
01HS1
10HS2
11HS3
Table 13. Slew Rate Speed Selection
SR1_s (D4) SR0_s (D3) Slew Rate Speed
0 0 medium (default)
01low
1 0 high
11Not used