Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 35
10XSC425
6.2.5 Normal and Fail-safe Mode Transitions
6.2.5.1 Transition Fail-safe to Normal Mode
To leave the Fail-safe mode, V
DD
must be in nominal voltage and the microcontroller has to send a SPI command with the WDIN
bit set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode
(autoretry included).
Moreover, the device can be brought out of the Fail-safe mode due to a watchdog timeout issue, by forcing the FSI pin to logic [0].
6.2.5.2 Transition Normal to Fail-safe Mode
To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into
Fail-safe mode (autoretry included).
6.2.6 Fault Mode
The 10XSC425 is in Fault mode when:
•V
PWR
and V
DD
are within the normal voltage range,
• wake-up = 1,
• fail = X,
•fault=1.
This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:
• Overtemperature fault,
• Overcurrent fault,
• Severe short-circuit fault,
• Output(s) shorted to VPWR fault in OFF state,
• OpenLoad fault in OFF state,
• Overvoltage fault (enabled by default),
• Undervoltage fault.
The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature, and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI
communication.
The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x])
and the
FSB pin.
6.2.7 Start-up Sequence
The 10XSC425 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds,
• generate wake-up event (wake-up = 1) from 0 to 1 on RSTB. The device switches to Normal mode with the SPI register
content reset (as defined in
Table 11 and Table 23). All features of the 10XSC425 will be available after 50 s (typical), and
all SPI registers are set to default values (set to logic [0]).
• toggle WD bit from 0 to 1.
And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• apply the PWM clock on the IN0 input pin after a maximum of 200 s (min. 50 s).
If the correct start-up sequence is not provided, the PWM function is not guaranteed.