Datasheet

Analog Integrated Circuit Device Data
34 Freescale Semiconductor
10XSC425
6.2.2.2 Calibratable Internal Clock
The internal clock can vary as much as 30%, corresponding to a typical f
PWM(0)
output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XSC425 allows clock period
setting within 10% accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is
provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin transitions
from a logic [1] to [0], until from a logic [0] to [1], determine the period of the internal clock with a multiplicative factor of 128.
In case a negative CSB pulse is outside a predefined time range (from t
CSB(MIN)
to t
CSB(MAX)
), the calibration event will be ignored
and the internal clock will be unaltered, or reset to the default value (f
PWM(0)
), if this was not calibrated before.
The calibratable clock is used instead of the clock from the IN0 input, when CLOCK_sel is set to [1].
6.2.3 Fail-safe Mode
The 10XSC425 is in Fail-safe mode when:
•V
PWR
is within the normal voltage range,
• wake-up = 1,
• fail = 1,
•fault = 0.
6.2.4 Watchdog
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE, or IN_ON[0:3], or RSTB input
pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to V
PWR
with a series of limiting resistance
limiting the internal clamp current according to the specification.
The Watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled
within the minimum watchdog timeout period (WDTO), the device will operate normally.
6.2.4.1 Fail-Safe Conditions
If an internal watchdog timeout occurs before the WD bit for FSI open (Table 9) or in case of a V
DD
failure condition (V
DD
<
V
DD(FAIL)
) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to a logic [1]
(see fail-safe to normal mode transition paragraph) and V
DD
is within the normal voltage range.
During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default
value (except POR bit) and fault protections are fully operational. The Fail-safe mode can be detected by monitoring the NM bit
is set to [0].
Table 9. SPI Watchdog Activation
Typical RFSI () Watchdog
0 (shorted to ground) Disabled
(open) Enable
CSB
SI
CALR
SI command
ignored
Internal
clock duration