Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 29
10XSC425
5.2.7 Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the 10XSC425 device. The serial input (SI) pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the serial output (SO) pin shifts data information out of the SO line driver
on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever
CSB makes any transition.
For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK
has an active internal pull-down. When
CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-
impedance) (see
Figure 10, page 31). SCLK input has an active internal pull-down, I
DWN
.
5.2.8 Serial Input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XSC425 are configured and
controlled using a 5-bit addressing scheme described in
Table 10. Register addressing and configuration are described in
Table 11. SI input has an active internal pull-down, I
DWN
.
5.2.9 Digital Drain Voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event V
DD
is lost (V
DD
Failure), the device
goes to Fail-safe mode.
5.2.10 Ground (GND)
These pins are the ground for the device.
5.2.11 Positive Power Supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the
backside surface mount tab of the package.
5.2.12 Serial Output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CSB pin
is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the
key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting
descriptions are provided in
Table 23.
5.2.13 High Side Outputs (HS3, HS1, HS0, HS2)
Protected 10 m and 25 m high side power outputs to the load.
5.2.14 Fail-safe Input (FSI)
This pin incorporates an active internal pull-up current source from internal supply (V
REG
). This enables the watchdog timeout
feature. When the FSI pin is opened, the Watchdog circuit is enabled. After a Watchdog timeout occurs, the output states
depends on IN[0:3]. When the FSI pin is connected to GND, the Watchdog circuit is disabled. The output states depends on
IN[0:3] in case of a V
DD
Failure condition. In case a V
DD
failure detection is activated (VDD_FAIL_en bit sets to logic [1]).