Datasheet

TJA1085 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 23 October 2012 30 of 61
NXP Semiconductors
TJA1085
FlexRay active star coupler
TEMP_WARN:
TEMP_WARN is set when the junction temperature rises above the temperature warning
level, generating a TEMP_ERROR interrupt.
If bit latching is enabled (BIT_LATCHING = 1), TEMP_WARN will remain set until the
General Status register has been read, after which it will reflect the current ‘live’ situation
(set when T
j
>T
j(warn)
and reset when T
j
<T
j(warn)
with no activity on the bus or on the CC
and TRXD0/1 interfaces). If bit latching is not enabled, TEMP_WARN will reflect the ‘live’
situation at all times.
TEMP_HIGH:
TEMP_HIGH is set when the junction temperature rises above the temperature high level.
The output driver on the TRXD0/1 interface is disabled along with the branch transmitters
(all branches switch to Branch_Disabled). A TEMP_ERROR interrupt is generated.
If bit latching is enabled (BIT_LATCHING = 1), TEMP_HIGH will remain set until the
General Status register has been read, after which it will reflect the current ‘live’ situation
(set when T
j
>T
j(high)
and reset when T
j
<T
j(high)
with no activity on the bus or on the CC
and TRXD0/1 interfaces). If bit latching is not enabled, TEMP_HIGH will reflect the ‘live’
situation at all times.
CLAMP_TRXD:
CLAMP_TRXD is set when the TRXD0/1 interface is configured as an input and TRXD0
or TRXD1 is clamped LOW for longer than t
detCL(TRXD)
. The output driver on the TRXD0/1
interface is disabled and data on the inputs is ignored. A CLAMP_ERROR interrupt is
generated.
If bit latching is enabled, CLAMP_TRXD will remain set until the General Status register
has been read, after which it will reflect the current ‘live’ situation (set when TRXD0 or
TRXD1 clamped LOW and reset when TRXD0 and TRXD1 are HIGH). If bit latching is not
enabled, CLAMP_TRXD will reflect the ‘live’ situation at all times.
CLAMP_TXEN:
CLAMP_TXEN is set when the TXEN is clamped LOW for longer than t
detCL(TXEN)
. Data
on TXD/TXEN is ignored and a CLAMP_ERROR interrupt is generated.
If bit latching is enabled, CLAMP_TXEN will remain set until the General Status register
has been read, after which it will reflect the current ‘live’ situation (set when TXEN
clamped LOW and reset when TXEN is HIGH). If bit latching is not enabled,
CLAMP_TXEN will reflect the ‘live’ situation at all times.
COLL_TRXD:
COLL_TRXD is set when a collision is detected on the TRXD0/1 interface (TRXD0 and
TRXD1 LOW for longer than t
det(col)(TRXD)
). A CLAMP_ERROR interrupt is generated.
COLL_TRXD is reset once the General Status register has been read.