Datasheet

Product data sheet Rev. 1 — 23 October 2012 26 of 61

NXP Semiconductors

TJA1085

FlexRay active star coupler

PWON: A PWON interrupt is generated to signal a power-on event.

The PWON interrupt status bit is set when the TJA1085 leaves AS_PowerOff or

AS_Reset. It is reset after a successful read operation on the Interrupt Status register.

WU: A WU interrupt indicates the occurrence of a wake-up event.

The WU interrupt status bit is set when a wake-up event is detected on a branch

(WU_BRx = 1), on TRXD0/1 (WU_TRXD = 1), or on LWU (WU_LOCAL = 1). It is reset

after a successful read operation on the Interrupt Status register.

EVENT_BRx: An EVENT_BRx interrupt signals the occurrence of a significant event on

the relevant branch.

The EVENT_BRx interrupt status bit is set when any of the following events is detected on

a branch:

- a wake-up event (WU_BRx = 1)

- a bus error (TxE_BRx = 1)

- clamping (CLAMP_BRx = 1)

It is reset after the flag (or flags) that triggered the interrupt has been reset and the

Interrupt Status register has been read successfully. Resetting EVENT_BRx will trigger a

falling edge on INTN to indicate to the host that the event that triggered the interrupt has

been resolved (except when the interrupt was triggered by a branch wake-up event).

UV_ERROR: A UV_ERROR interrupt indicates that an undervoltage has occurred.

The UV_ERROR interrupt status bit is set when a V

BAT

(UV_VBAT = 1), V

(UV_VCC = 1) or V

(UV_VIO = 1) undervoltage is detected. It is reset after the flag (or

flags) that triggered the interrupt has been reset and the Interrupt Status register has been

read successfully. Resetting UV_ERROR triggers a falling edge on INTN to indicate to the

host that the undervoltage condition is no longer present.

CLAMP_ERROR: A CLAMP_ERROR interrupt indicates that an input channel has

become clamped or a collision has occurred on the TRXDO/1 interface.

The CLAMP_ERROR interrupt status bit is set when clamping is detected on TRXD

(CLAMP_TRXD = 1), on TXEN (CLAMP_TXEN = 1) or on a branch (CLAMP_BRx = 1) or

if a collision is detected on TRXD0/TRXD1 (COLL_TRXD = 1). It is reset after the flag (or

flags) that triggered the interrupt has been reset and the Interrupt Status register has been

read successfully. Resetting CLAMP_ERROR triggers a falling edge on INTN to indicate

to the host that the clamp or collision error has been corrected.

SPI_ERROR: An SPI_ERROR interrupt indicates that an error has occurred during SPI

communications.

The SPI_ERROR interrupt status bit is set if the number of SCLK cycles generated during

a LOW phase on SCSN does not equal 16. It is reset after a successful read operation on

the Interrupt Status register.

HC_ERROR: A HC_ERROR interrupt indicates that an invalid host command has been

received.