Datasheet

TJA1085 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 23 October 2012 20 of 61
NXP Semiconductors
TJA1085
FlexRay active star coupler
6.10 SPI interface
The TJA1085 contains a bidirectional 16-bit Serial Peripheral Interface (SPI) for
communicating with a host. The SPI allows the host to configure the TJA1085 and to
access error and status information.
6.10.1 Register access
The SPI supports full duplex data transfer, so status information is read out on pin SDO
while control data is being shifted in on pin SDI. Bit sampling is performed on the falling
edge of the clock signal on pin SCLK and data is shifted on the rising edge (MSB first; see
Figure 8
).
The clock signal must be LOW when SCSN goes LOW to initiate an SPI register access
cycle.
6.10.2 SPI registers
The SPI register structure in the TJA1085 is illustrated in Figure 9. The three MSBs
(bits15 to 13) contain the 3-bit register address. Bit 12 defines the selected register
access as read/write or read only. If bit 12 is 1, the SPI data transfer will be read only and
all data on the SDI pin will be ignored. If bit 12 is 0, data bits 11 to 0 will be written to the
selected register.
Fig 8. SPI register access
SCSN
SCLK
01
sampled
floating floating
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X
X
MSB 14 13 12 01 LSB
MSB 14 13 12 01 LSB
X
SDI
SDO
02 03 04 15 16
Fig 9. SPI register structure
15
0
Data BitsRegister Select
Bits 15 to 13: register address
Bit 12: 1 = R/O (read only), 0 = R/W (read/write)
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