Datasheet

TJA1021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 25 March 2011 4 of 25
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is
recommended that the exposed center pad also be soldered to board ground.
a. TJA1021T/10; TJA1021T/20: SO8 b. TJA1021TK/10; TJA1021TK/20:
HVSON8
Fig 2. Pin configuration diagrams
TJA1021T
RXD INH
SLP_N V
BAT
WAKE_N
LIN
TXD GND
015aaa231
1
2
3
4
6
5
8
7
015aaa232
TJA1021TK
GND
WAKE_N
TXD
LIN
SLP_N V
BAT
RXD INH
Transparent top view
4
5
3 6
2 7
1 8
terminal 1
index area
Table 3. Pin description
Symbol Pin Description
RXD 1 receive data output (open-drain); active LOW after a wake-up event
SLP_N 2 sleep control input (active LOW); controls inhibit output; resets
wake-up source flag on TXD and wake-up request on RXD
WAKE_N 3 local wake-up input (active LOW); negative edge triggered
TXD 4 transmit data input; active LOW output after a local wake-up event
GND 5
[1]
ground
LIN 6 LIN bus line input/output
V
BAT
7 battery supply voltage
INH 8 battery related inhibit output for controlling an external voltage
regulator; active HIGH after a wake-up event