Datasheet

TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3.1 — 13 December 2012 8 of 30
NXP Semiconductors
TDA8034T; TDA8034AT
Smart card interface
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
V
CC
and/or between pins I/OUC and V
DD(INTF)
, both lines enter the idle state. Pin I/O is
referenced to V
CC
and pin I/OUC to V
DD(INTF)
, thus allowing operation at V
CC
 V
DD(INTF)
.
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay t
d
,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (t
w(pu)
). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the
TDA8034T/TDA8034AT capable of delivering more than 1 mA, up to an output voltage of
0.9V
CC
, at a load of 80 pF. At the end of the active pull-up pulse, the output voltage is
dependent on the internal pull-up resistor value and load current. The current sent to and
received from the card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.