Datasheet

TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.2 — 25 March 2014 9 of 30
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.7 Activation sequence
The following device activation sequence is applied when using an external clock; see
Figure 7
:
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. V
CC
rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
Calculation of the time delays is as follows:
• t1 = t0 + 384 
1
⁄
fosc(int)low
• t2 = t1
• t3 = t1 + 17T / 2
• t4 = driven by host controller; > t3 and < t5
• t5 = t1 + 23T / 2
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (
1
⁄
fosc(int)high
); t3 is called t
d(start)
and t5 is called t
d(end)
.
Fig 6. Shutdown and Deep shutdown mode activation/deactivation
001aal139
shutdown
CMDVCCN
VCC_SEL1
VCC_SEL2
mode
(internal pin)
OFFN
PRESN
V
CC
shutdown
deactivation
sequence
shutdown
debounce
deep shutdownactivation activation