Datasheet

TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.2 — 25 March 2014 7 of 30
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034HN automatically detects if an external clock is connected to
XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either f
xtal
,
1
⁄
2
f
xtal
or
1
⁄
4
f
xtal
or
1
⁄
8
f
xtal
as shown in Table 4.
Remark: The levels on both pins must not be allowed to change simultaneously but
should be separated by a minimum of 10 ns.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f
xtal
on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either f
xtal
,
1
⁄
2
f
xtal
,
1
⁄
4
f
xtal
or
1
⁄
8
f
xtal
,
the frequency dividers guarantee a duty cycle between 45 % and 55 %.
enclkin and clkxtal are internal signal names.
Fig 5. Basic layout for using an external clock
Table 4. Clock configuration
Pin CLKDIV1 level Pin CLKDIV2 level Pin CLK frequency
LOW LOW
1
⁄
8
f
xtal
LOW HIGH
1
⁄
4
f
xtal
HIGH HIGH
1
⁄
2
f
xtal
HIGH LOW f
xtal
001aak992
DIGITAL
MULTIPLEXER
CRYSTAL
XTAL1 XTAL2
clkxtalenclkin