Datasheet
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.2 — 25 March 2014 4 of 30
NXP Semiconductors
TDA8034HN
Low power smart card interface
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration
001aal137
TDA8034HN
Transparent top view
CLK
CMDVCCN
CLKDIV1
RST
VCC_SEL1 V
CC
RSTIN V
DDP
VCC_SEL2 V
DD
V
DD(INTF)
PORADJ
CLKDIV2
PRESN
I/O
AUX1
AUX2
GND
XTAL2
XTAL1
AUX2UC
AUX1UC
I/OUC
OFFN
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
Table 3. Pin description
Symbol Pin Supply Type
[1]
Description
V
DD(INTF)
1V
DD(INTF)
P interface supply voltage
VCC_SEL2 2 V
DD(INTF)
I5V or 3V V
CC
voltage selection control signal:
active LOW: V
CC
= 3 V when pin VCC_SEL1 is HIGH
active HIGH: V
CC
= 5 V
RSTIN 3 V
DD(INTF)
I microcontroller card reset input; active HIGH
VCC_SEL1 4 V
DD(INTF)
I 1.8 V V
CC
voltage selection control signal:
active LOW: V
CC
= 1.8 V
active HIGH: disables 1.8 V selection
CMDVCCN 5 V
DD(INTF)
I microcontroller start activation sequence input; active LOW
CLKDIV1 6 V
DD(INTF)
I sets the clock frequency on pin CLK in association with pin CLKDIV2; see Table 4
CLKDIV2 7 V
DD(INTF)
I sets the clock frequency on pin CLK in association with pin CLKDIV1; see Table 4
PRESN 8 V
DD(INTF)
I card presence contact input; active LOW
[2]
I/O 9 V
CC
I/O card input/output data line (C7)
[3]
AUX1 10 V
CC
I/O auxiliary card input/output data line (C4)
[3]
AUX2 11 V
CC
I/O auxiliary card input/output data line (C8)
[3]
GND 12 - G ground
CLK 13 V
CC
O card clock (C3)
RST 14 V
CC
O card reset (C2)
V
CC
15 V
CC
P card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin V
CC
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m