Datasheet

TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.2 — 25 March 2014 19 of 30
NXP Semiconductors
TDA8034HN
Low power smart card interface
[1] To meet these specifications, V
CC
should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of
one 220 nF and one 470 nF.
[2] Using decoupling capacitors of one 220 nF 20 % and one 470 nF 20 %.
[3] Using the integrated 9 k pull-up resistor connected to V
CC
.
[4] Using the integrated 10 k pull-up resistor connected to V
DD(INTF)
.
[5] The transition time and the duty factor definitions are shown in Figure 11 on page 19
;  = t1 / (t1 + t2).
[6] Pins PRESN and CMDVCCN are active LOW; pin RSTIN is active HIGH; see Table 4
for states of pins CLKDIV1 and CLKDIV2.
[7] Pin PRESN has an integrated current source of 1.25 A to V
DD(INTF)
.
[8] Pin OFFN is an NMOS drain, using an internal 20 k pull-up resistor connected to V
DD(INTF)
.
Table 8. Protection characteristics
Symbol Parameter Conditions Min Typ Max Unit
I
Olim
output current limit pin I/O 15 - +15 mA
pin V
CC
135 175 225 mA
pin CLK 70 - +70 mA
pin RST 20 - +20 mA
I
sd
shutdown current pin V
CC
90 120 150 mA
T
sd
shutdown temperature at die - 150 - C
Table 9. Timing characteristics
Symbol Parameter Conditions Min Typ Max Unit
t
act
activation time see Figure 7 on page 10 2090 - 4160 s
t
deact
deactivation time see Figure 8 on page 11 35 90 250 s
t
d
delay time CLK sent to card using an external clock
t
d(start)
= t3; see Figure 7 on page 10 2090 - 4112 s
t
d(end)
= t5; see Figure 7 on page 10 2120 - 4160 s
t
deb
debounce time pin PRESN 3.2 4.5 6.4 ms
Fig 11. Definition of output and input transition times
001aai973
10 % 10 %
90 % 90 %
t
r
t
f
V
OH
(V
OH
+ V
OL
) / 2
V
OL
t1 t2