Datasheet

TDA8023_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 16 July 2007 21 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
t
r
rise time input; from V
IL(max)
to V
IH(min)
--1 µs
t
TLH
clock rise time output transition time; from
10 % to 90 % of V
DD(INTF)
;
C
L
<30pF
- - 0.1 µs
R
pu(int)
internal pull-up resistance between pin I/OUC and pin
V
DDI
[1]
11 15 19 kΩ
Clock input: pin CLKIN
f
CLKIN
frequency on pin CLKIN 0 - 25 MHz
V
IL
LOW-level input voltage V
DD(INTF)
> 2 V 0 - 0.3V
DD(INTF)
V
1.5 V < V
DD(INTF)
< 2 V 0 - 0.15V
DD(INTF)
V
V
IH
HIGH-level input voltage V
DD(INTF)
> 2 V 0.7V
DD(INTF)
-V
DD(INTF)
+ 0.3 V
1.5 V < V
DD(INTF)
< 2 V 0.85V
DD(INTF)
-V
DD(INTF)
+ 0.3 ns
t
r
rise time - - 0.1 / f
CLKIN
ns
t
f
fall time - - 0.1 / f
CLKIN
ns
Logic inputs: pins SAD0, SPRES and SDWN
V
IL
LOW-level input voltage −0.3 - 0.3V
DD(INTF)
V
V
IH
HIGH-level input voltage 0.7V
DD
-V
DD(INTF)
+ 0.3 V
I
LIL
LOW-level input leakage
current
--±1 µA
I
LIH
HIGH-level input leakage
current
--±1 µA
C
i
input capacitance - - 10 pF
Interrupt line: pin
INT; open-drain active-LOW output
V
OL
LOW-level output voltage I
o
= 2 mA - - 0.3 V
I
LH
HIGH-level leakage current - - 10 µA
Serial data input/output: pin SDA; open-drain
V
IL
LOW-level input voltage −0.3 - 0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
- 6.5 V
V
OL1
LOW-level output voltage I
OL
= 3 mA - - 0.3 V
I
LH
HIGH-level leakage current input or output - - 1 µA
I
LL
LOW-level leakage current depends on the pull-up
resistance; input or output
--1 µA
Serial clock input: pin SCL
V
IL
LOW-level input voltage −0.3 - 0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
- 6.5 V
I
LIH
HIGH-level input leakage
current
--1 µA
I
IL
LOW-level input current depends on the pull-up
resistance
--1 µA
Table 20. Interface signals to host controller
…continued
V
DD
= 3.3 V; V
DD(INTF)
= 1.5 V; f
CLKIN
= 10 MHz; GND = 0 V; T
amb
= 25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit