Datasheet

TDA8023_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 16 July 2007 15 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
8.6.2 Deactivation sequence
When the session is completed, the microcontroller resets bit START to logic 0 (t
10
, see
Figure 6). The circuit then executes an automatic deactivation sequence:
1. Card reset: pin RST falls to LOW (t
11
).
2. CLK is stopped (t
12
).
3. Pin I/O falls to 0 V (t
13
).
4. Pin V
CC
falls to 0 V with a controlled slew rate (t
14
).
5. The DC-to-DC converter is stopped and pins CLK, RST, V
CC
and I/O become
low-impedance with relation to GNDC (t
15
).
6. The internal oscillator changes to its low frequency (t
15
).
, , , and .
The deactivation time t
deact
is the time that V
CC
needs for going down to less than 0.4 V,
counted from the moment bit START is reset.
8.7 Protection
All card contacts are protected against any short with any other card contact.
The currents on various pins are limited:
• on pin CLK: limited to ±70 mA
• on pin I/O: limited to ±10 mA (typical value)
• on pin RST: limited (only when this pin is LOW) to ±20 mA
• on pin V
CC
: limited to 90 mA
If any of these currents exceeds its limit, an emergency deactivation sequence is
performed: pin INT is pulled LOW and bit PROT in the Status register is set.
Fig 6. Deactivation sequence
t
11
t=
10
T
64
------
+ t
12
t=
11
T
2
---
+ t
13
t=
11
T+ t
14
t=
11
3T
2
-------
+ t
15
t
11
=
7T
2
-------
+
START
VUP
V
CC
I/O
CLK
RST
t
10
t
12
t
13
t
deact
t
14
t
15
t
11
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