Datasheet
TDA8023_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 16 July 2007 14 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
When everything is satisfactorily present (voltage supply, card present, no hardware
problems) the system controller may initiate an activation sequence of a present card:
1. The internal oscillator changes to its high frequency (t
0
, see Figure 5).
2. The DC-to-DC converter is started (t
1
).
3. V
CC
starts rising from 0 V to 5 V, 3 V or 1.8 V with a controlled rise time (t
2
).
4. The voltage on pin I/O rises to V
CC
, due to integrated 14 kΩ pull-ups to V
CC
(t
3
).
5. CLK is sent to the card and pin RST is enabled (t
4
= t
act
).
During the activation sequence, the answer from the card (ATR) is monitored and the
steps are the following:
1. If a start bit is detected on pin I/O during the first 200 CLK pulses, then it is simply
ignored, and the CLK count goes on.
2. If a start bit is detected whilst pin RST = LOW (between 200 and 42100 CLK pulses or
the value written in C[15:0]), then the bits EARLY and MUTE are set in the Status
register. Pin RST will remain LOW. It is up to the software to decide whether to accept
the card or not.
3. If no start bit has been detected within 42100 CLK pulses, then pin RST is toggled to
HIGH (t
5
).
4. If, again, a start bit is detected within 370 CLK pulses (200 + 170 or the value defined
in D[7:0]), bit EARLY in the Status register is set.
5. If the card does not answer within 42100 new CLK pulses, then bit MUTE in the
Status register is set.
6. If the card answers within the correct time window, then the CLK count is stopped and
the system controller can send commands to the card.
The sequencer is clocked by which leads to a time interval T = 25 µs (typical).
Thus s to , , and .
Fig 5. Activation sequence
f
osc int()
64
-------------------
t
1
0=
T
64
------
t
2
t=
1
3T
2
-------
+ t
3
t
1
=
7T
2
-------
+ t
4
t=
1
4T+
001aag340
t
act
START
VUP
V
CC
I/O
CLK
RST
t
1
t
0
t
2
t
3
t
4
t
5
ATR