Datasheet

TDA8023_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 16 July 2007 11 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
[1] Synchronous or asynchronous cards management are defined when bit START is set: the TDA8023 will be
in asynchronous cards management when bit RSTIN = 1 when bit START is set to logic 1.
3 PDWN 1: applies on pin CLK the frequency that is defined by bits CLKPD[2:1]
and reduces power consumption (in Synchronous mode); this bit can not
change if bit START is logic 1
2 5V/3VN 1: V
CC
= 5 V
0: V
CC
= 3 V
this bit can not change if bit START is logic 1
1 WARM 1: initiates a warm reset procedure
this bit will be automatically reset by hardware when bit MUTE is set to
logic 1
0 START 1: initiates an activation sequence and a cold reset procedure (only if bit
SUPL = 0 and the bit PRES = 1)
0: initiates a deactivation sequence
Table 9. R1_00 - Register 1 subaddress 00 in Read/Write mode bit description
Bit Symbol Description
7 TEST 1: the circuit is in Test mode
0: the circuit is in Operational mode
6 RSTIN
[1]
defines the voltage on pin RST:
1: V
CC
0: 0 V
5 C8 defines the voltage on pin C8:
1: V
CC
0: 0 V
4 C4 defines the voltage on pin C4:
1: V
CC
0: 0 V
3 and 2 CLKPD[2:1] clock pulse definition:
00: CLK stop LOW
01: CLK stop HIGH
10: frequency on pin CLK: f
CLK
= f
osc(int)
/ 2
11: no change
in Synchronous mode bit CLKPD2 is always logic 0 by hardware and bit
CLKPD1 controls the voltage on pin CLK:
1: V
CC
0: 0 V
1 and 0 CLKDIV[2:1] clock divider:
00: f
CLK
= f
CLKIN
01: f
CLK
= f
CLKIN
/ 2
10: f
CLK
= f
CLKIN
/ 4
11: f
CLK
= f
CLKIN
/ 5
in Synchronous mode, bits CLKDIV[2:1] are always 00 by hardware
Table 8. Command - Register 0 in Write mode bit description
…continued
Bit Symbol Description