Datasheet

TDA8023_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 16 July 2007 10 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
8.3.5 Registers
When at least one of the bits PRESL, PROT, MUTE and EARLY is set, pin INT goes LOW
until the status byte has been read. After power-on, bit SUPL is set until the status byte
has been read, and pin INT = LOW until the voltage supervisor becomes inactive.
Table 6. Table of registers
Bit Register 0 Register 1
Read mode Write mode Read/Write mode
Status Command REG1 = 0 REG1 = 1
REG0 = 0 REG0 = 1 REG0 = 0 REG0 = 1
7 ACTIVE VCC1V8 TEST D7 C15 C7
6 EARLY I/OEN RSTIN D6 C14 C6
5 MUTE REG1 C8 D5 C13 C5
4 PROT REG0 C4 D4 C12 C4
3 SUPL PDWN CLKPD2 D3 C11 C3
2 CLKSW 5V/3VN CLKPD1 D2 C10 C2
1 PRESL WARM CLKDIV2 D1 C9 C1
0 PRES START CLKDIV1 D0 C8 C0
Table 7. Status - Register 0 in Read mode bit description
Bit Symbol Description
7 ACTIVE set if the card is active; reset if the card is inactive
6 EARLY set during Answer To Reset (ATR) when the selected card has answered
too early
5 MUTE set during ATR when the card has not answered during the ISO 7816
time slots
4 PROT set when an overload or an overheating has occurred during a session;
reset when the status has been read
3 SUPL set when the voltage supervisor has signalled a fault; reset when the
status has been read
2 CLKSW set when the TDA8023 is in Power-down mode and the clock has
changed
1 PRESL set when the card has been inserted or extracted; reset when the status
has been read
0 PRES set when the card is present; reset when the card is not present
Table 8. Command - Register 0 in Write mode bit description
Bit Symbol Description
7 VCC1V8 1: V
CC
= 1.8 V
0: V
CC
is defined by bit 5V/3VN
this bit can not change if bit START is logic 1
6 I/OEN 1: signal on pin I/OUC is transferred to pin I/O
0: pin I/OUC and pin I/O are high-impedance
5 and 4 REG[1:0] selection of subaddress in Register 1 (see
Table 9, 10, 11 and 12)