Datasheet

PEMD2_PIMD2_PUMD2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 14 November 2013 3 of 18
NXP Semiconductors
PEMD2; PIMD2; PUMD2
NPN/PNP resistor-equipped transistors; R1 = 22 k, R2 = 22 k
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter - 50 V
V
CEO
collector-emitter voltage open base - 50 V
V
EBO
emitter-base voltage open collector - 10 V
V
I
input voltage TR1
positive - +40 V
negative - 10 V
input voltage TR2
positive +10
negative 40
I
O
output current - 100 mA
I
CM
peak collector current single pulse;
t
p
 1ms
-100mA
P
tot
total power dissipation T
amb
 25 C
PEMD2 (SOT666)
[1]
-200mW
PIMD2 (SOT457)
[1]
250 mW
PUMD2 (SOT363)
[1]
-200mW
Per device
P
tot
total power dissipation T
amb
 25 C
PEMD2 (SOT666)
[1]
-300mW
PIMD2 (SOT457)
[1]
400 mW
PUMD2 (SOT363)
[1]
-300mW
T
j
junction temperature - 150 C
T
amb
ambient temperature 55 +150 C
T
stg
storage temperature 65 +150 C