Datasheet

PEMD3_PIMD3_PUMD3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 25 September 2013 3 of 18
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor (TR2) with negative polarity
V
CBO
collector-base voltage open emitter - 50 V
V
CEO
collector-emitter voltage open base - 50 V
V
EBO
emitter-base voltage open collector - 10 V
V
I
input voltage TR1
positive - +40 V
negative - 10 V
input voltage TR2
positive - +10 V
negative - 40 V
I
O
output current - 100 mA
I
CM
peak collector current - 100 mA
P
tot
total power dissipation T
amb
 25 C
[1]
PEMD3 (SOT666) - 200 mW
PIMD3 (SOT457) - 250 mW
PUMD3 (SOT363) - 200 mW
Per device
P
tot
total power dissipation T
amb
 25 C
[1]
PEMD3 (SOT666) - 300 mW
PIMD3 (SOT457) - 400 mW
PUMD3 (SOT363) - 300 mW
T
j
junction temperature - 150 C
T
amb
ambient temperature 65 +150 C
T
stg
storage temperature 65 +150 C