Datasheet

PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 5 of 33
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
7. Functional description
Refer to Figure 1 “Block diagram”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address format of the
PCF8574/74A is shown in Figure 6
. Slave address pins A2, A1 and A0 are held HIGH or
LOW to choose one of eight slave addresses. To conserve power, no internal pull-up
resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW.
The address pins (A2, A1, A0) can connect to V
DD
or V
SS
directly or through resistors.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation (write operation is shown in
Figure 6
).
7.1.1 Address maps
The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion
(A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the
PCF8574A to be on the same I
2
C-bus without address conflict.
a. PCF8574 b. PCF8574A
Fig 6. PCF8574 and PCF8574A slave addresses
R/W
002aad628
0 1 0 0 A2 A1 A0
hardware
selectable
slave address
0
fixed
R/W
002aad629
0 1 1 1 A2 A1 A0
hardware
selectable
slave address
0
fixed
Table 4. PCF8574 address map
Pin connectivity Address of PCF8574 Address byte value 7-bit
hexadecimal
address
without R/W
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
V
SS
V
SS
V
SS
0100000 - 40h 41h 20h
V
SS
V
SS
V
DD
0100001 - 42h 43h 21h
V
SS
V
DD
V
SS
0100010 - 44h 45h 22h
V
SS
V
DD
V
DD
0100011 - 46h 47h 23h
V
DD
V
SS
V
SS
0100100 - 48h 49h 24h
V
DD
V
SS
V
DD
0100101 - 4Ah 4Bh 25h
V
DD
V
DD
V
SS
0100110 - 4Ch 4Dh 26h
V
DD
V
DD
V
DD
0100111 - 4Eh 4Fh 27h