Datasheet
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 29 of 33
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
21. Revision history
Table 15. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8574_PCF8574A v.5 20130527 Product data sheet - PCF8574 v.4
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Electrical parameter letter-symbols and their definitions are updated to conform to NXP
presentation standards.
• Section 1 “General description”: updated
• Section 2 “Features and benefits”:
– third bullet item: appended “with non-overvoltage tolerant I/O held to V
DD
with 100 A
current source”
– added (new) fourth and seventh bullet items
– added sixth bullet item: “Total package sink capability of 80 mA”
– ninth bullet changed from “(10 A maximum)” to “(2.5 A typical)”
– deleted (old) 11th, 12th and 13th bullet items
• Added (new) eighth bullet item “Mobile devices”
• Table 1 “Ordering information”:
– Type number corrected from “PCF8574T” to “PCF8574/3”
– Type number corrected from “PCF8574AT” to “PCF8574AT/3”
– Type number corrected from “PCF8574TS” to “PCF8574TS/3”
– Type number corrected from “PCF8574ATS” to “PCF8574ATS/3”
• Added Section 4.1 “Ordering options”
• Figure 4 “Pin configuration for SO16”: updated type numbers (appended “/3”)
• Figure 5 “Pin configuration for SSOP20”: updated type numbers (appended “/3”)
• Section 6.2 “Pin description”: combined DIP16, SO16 and SSOP20 pin descriptions into
one table (Table 3
)
• Section 7 “Functional description” reorganized
• Section 7.1 “Device address”, first paragraph, fourth sentence: appended “so they must be
externally held HIGH or LOW”
• Table 4 “PCF8574 address map” updated: added column for 7-bit hexadecimal address
without R/W
• Table 5 “PCF8574A address map” updated: added column for 7-bit hexadecimal address
without R/W
• Section 8.1 “Quasi-bidirectional I/Os”: re-written and placed before Section 8.4 “Power-on
reset”
• added Section 8.2 “Writing to the port (Output mode)”
• added Section 8.3 “Reading from a port (Input mode)”
• Figure 9 “Read mode (input)”: changed symbol “t
ps
” to “t
su
”
• Section 8.4 “Power-on reset” re-written
• Section 8.5 “Interrupt output (INT)” re-written
• Figure 10 “Application of multiple PCF8574/74As with interrupt” updated: changed
device 16 from “PCF8574” to “PCF8574A”
• Section 9.3 “Acknowledge”, first paragraph, third sentence re-written.
• Added Section 10 “Application design-in information”