Datasheet

PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 17 of 33
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I
2
C-bus with interrupt
14. Dynamic characteristics
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
Table 10. Dynamic characteristics
V
DD
= 2.5 V to 6 V; V
SS
=0V; T
amb
=  40  C to +85  C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
I
2
C-bus timing
[1]
(see Figure 17)
f
SCL
SCL clock frequency - - 100 kHz
t
BUF
bus free time between a STOP and
STARTcondition
4.7 - - s
t
HD;STA
hold time (repeated) START condition 4 - - s
t
SU;STA
set-up time for a repeated START condition 4.7 - - s
t
SU;STO
set-up time for STOP condition 4 - - s
t
HD;DAT
data hold time 0 - - ns
t
VD;DAT
data valid time - - 3.4 s
t
SU;DAT
data set-up time 250 - - ns
t
LOW
LOW period of the SCL clock 4.7 - - s
t
HIGH
HIGH period of the SCL clock 4 - - s
t
r
rise time of both SDA and SCL signals - - 1 s
t
f
fall time of both SDA and SCL signals - - 0.3 s
Port timing (see Figure 8
and Figure 9)
t
v(Q)
data output valid time C
L
 100 pF - - 4 s
t
su(D)
data input set-up time C
L
 100 pF 0 - - s
t
h(D)
data input hold time C
L
 100 pF 4 - - s
Interrupt INT
timing (see Figure 9)
t
v(INT)
valid time on pin INT from port to INT;
C
L
 100 pF
--4s
t
rst(INT)
reset time on pin INT from SCL to INT;
C
L
 100 pF
--4s