Datasheet

PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 3 October 2012 37 of 48
NXP Semiconductors
PCAL9539A
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
a. SDA load configuration b. P port load configuration
c. RESET
timing
C
L
includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z
o
=50; t
r
/t
f
 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig 32. Reset load circuits and voltage waveforms
002aag803
DUT
C
L
= 50 pF
R
L
= 1 kΩ
SDA
V
DD
002aag805
DUT
C
L
= 50 pF
500 Ω
Pn
2 × V
DD
500 Ω
SDA
SCL
002aah073
t
rst
t
rec(rst)
t
w(rst)
RESET
Pn
START
t
rst
ACK or read cycle
0.3 × V
DD
0.5 × V
DD
0.5 × V
DD
t
rec(rst)