Datasheet
PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 3 October 2012 2 of 48
NXP Semiconductors
PCAL9539A
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
2. Features and benefits
I
2
C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5 A (typical at 5 V V
DD
)
1.0 A (typical at 3.3 V V
DD
)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
V
hys
= 0.10 V
DD
(typical)
5 V tolerant I/Os
Active LOW reset input (RESET
)
Open-drain active LOW interrupt output (INT
)
400 kHz Fast-mode I
2
C-bus
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HVQFN24
2.1 Agile I/O features
Pin to pin replacement for PCA9539 and PCA9539A with interrupts disabled at
power-up
Software backward compatible with PCA9539 and PCA9539A
Output port configuration: bank selectable push-pull or open-drain output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
Output drive strength: four programmable drive strengths to reduce rise and fall
times in low capacitance applications
Input latch: Input Port register values changes are kept until the Input Port register
is read
Pull-up/pull-down enable: floating input or pull-up/down resistor enable
Pull-up/pull-down selection: 100 k pull-up/down resistor selection
Interrupt mask: mask prevents the generation of the interrupt when input changes
state