Datasheet

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PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 3 October 2012 18 of 48 NXP Semiconductors
PCAL9539A
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
Fig 10. Read input port register (input latch disabled), scenario 1
1101A1A01AS1
START condition
R/W
acknowledge
from slave
002aah407
A
SCL
SDA A
read from port 0
P
987654321
I0.xslave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
65432107 65432107 65432107 65432107
INT
t
v(INT)
t
rst(INT)