Datasheet

Product data sheet Rev. 1 — 3 October 2012 15 of 48

NXP Semiconductors

PCAL9539A

16-bit I

C-bus and SMBus low power I/O port with interrupt and reset

7. Bus transactions

The PCAL9539A is an I

C-bus slave device. Data is exchanged between the master and

PCAL9539A through write and read commands using I

C-bus. The two communication

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Writing to the port registers

Data is transmitted to the PCAL9539A by sending the device address and setting the least

significant bit to a logic 0 (see Figure 4 “

PCAL9539A device address”). The command

byte is sent after the address and determines which register will receive the data following

the command byte.

Twenty-two registers within the PCAL9539A are configured to operate as eleven register

pairs. The eleven pairs are input port, output port, polarity inversion, configuration,

output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable,

pull-up/pull-down selection, interrupt mask, and interrupt status registers. After sending

data to one register, the next data byte is sent to the other register in the pair (see Figure 7

and Figure 8

). For example, if the first byte is sent to Output Port 1 (register 3), the next

byte is stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this

way, the host can continuously update a register pair independently of the other registers,

or the host can simply update a single register.