Datasheet

PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 3 October 2012 14 of 48
NXP Semiconductors
PCAL9539A
16-bit I
2
C-bus and SMBus low power I/O port with interrupt and reset
6.4 Power-on reset
When power (from 0 V) is applied to V
DD
, an internal power-on reset holds the
PCAL9539A in a reset condition until V
DD
has reached V
POR
. At that time, the reset
condition is released and the PCAL9539A registers and I
2
C-bus/SMBus state machine
initializes to their default states. After that, V
DD
must be lowered to below V
PORF
and back
up to the operating voltage for a power-reset cycle. See Section 8.3 “
Power-on reset
requirements”.
6.5 RESET input
The RESET input can be asserted to initialize the system while keeping the V
DD
at its
operating level. A reset can be accomplished by holding the RESET
pin LOW for a
minimum of t
w(rst)
. The PCAL9539A registers and I
2
C-bus/SMBus state machine are
changed to their default state once RESET
is LOW (0). When RESET is HIGH (1), the I/O
levels at the ports can be changed externally or through the master. This input requires a
pull-up resistor to V
DD
if no active connection is used.
6.6 Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
v(INT)
, the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read form the port that generated the
interrupt (see Figure 10
). Resetting occurs in the Read mode at the acknowledge (ACK)
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT
.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT
output has an open-drain structure and requires pull-up resistor to V
DD
.
When using the input latch feature, the input pin state is latched. The interrupt is reset only
when data is read from the port that generated the interrupt. The reset occurs in the Read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of
the SCL signal.