Datasheet

Product data sheet Rev. 2 — 23 January 2015 8 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I

C-bus I/O port with interrupt and Agile I/O

6.2.4 Polarity inversion register pair (04h, 05h)

The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined

as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the

corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is

cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair

write is described in Section 7.1

and a register pair read is described in Section 7.2.

6.2.5 Configuration register pair (06h, 07h)

The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a

bit in these registers is set to 1, the corresponding port pin is enabled as a

high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin

is enabled as an output. A register pair write is described in Section 7.1

and a register pair

read is described in Section 7.2

Table 9. Polarity inversion port 0 register (address 04h)

Bit 7 6 5 4 3 2 1 0

Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

Default 00000000

Table 10. Polarity inversion port 1 register (address 05h)

Bit 7 6 5 4 3 2 1 0

Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

Default 00000000

Table 11. Configuration port 0 register (address 06h)

Bit 7 6 5 4 3 2 1 0

Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

Default 11111111

Table 12. Configuration port 1 register (address 07h)

Bit 7 6 5 4 3 2 1 0

Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

Default 11111111