Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 5 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
[1] HWQFN24 package die supply ground is connected to both V
SS
pin and exposed center pad. V
SS
pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
6. Functional description
Refer to Figure 1 “Block diagram of PCAL9535A”.
6.1 Device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W
) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9535A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in
conjunction with the lower four bits of the Command byte are used to point to the
extended features of the device (Agile I/O). This register is write only.
P1_7
[3]
20 17 I/O Port 1 input/output 7.
A0 21 18 I Address input 0. Connect directly to V
DD
or V
SS
.
SCL 22 19 I Serial clock bus. Connect to V
DD
through a
pull-up resistor.
SDA 23 20 I/O Serial data bus. Connect to V
DD
through a
pull-up resistor.
V
DD
24 21 power Supply voltage.
Table 3. Pin description
…continued
Symbol Pin Type Description
TSSOP24 HWQFN24
Fig 4. PCAL9535A device address
R/W
002aah371
0 1 0 0 A2 A1 A0
hardware
selectable
slave address
fixed