Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 34 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
a. Interrupt load configuration
b. Voltage waveforms
C
L
includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z
o
=50; t
r
/t
f
 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 30. Interrupt load circuit and voltage waveforms
002aah069
DUT
C
L
= 100 pF
R
L
= 4.7 kΩ
INT
V
DD
1 0 0 A2 A1 A0 1 AS0
slave address
START condition R/W
acknowledge
from slave
002aah256
8 bits (one data byte)
from port
A
acknowledge
from slave
SDA 1
no acknowledge
from master
data into
port
data from port
DATA 1
DATA 2
INT
DATA 2
DATA 1
P
STOP
condition
t
v(INT)
t
rst(INT)
t
su(D)
12345678SCL 9
ADDRESS
t
rst(INT)
A
A
View A - A
INT
Pn
t
v(INT)
0.5 × V
DD
0.5 × V
DD
View B - B
SCL
0.5 × V
DD
INT
R/W A
t
rst(INT)
0.3 × V
DD
0.7 × V
DD
B
B