Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 32 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
13. Dynamic characteristics
Table 33. I
2
C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Unit
Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
HIGH
HIGH period of the SCL clock 4 - 0.6 - s
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - s
t
SP
pulse width of spikes that must
be suppressed by the input filter
050 0 50ns
t
SU;DAT
data set-up time 250 - 100 - ns
t
HD;DAT
data hold time 0 - 0 - ns
t
r
rise time of both SDA and SCL signals - 1000 20 300 ns
t
f
fall time of both SDA and SCL signals - 300 20 
(V
DD
/5.5V)
300 ns
t
BUF
bus free time between a STOP and
START condition
4.7 - 1.3 - s
t
SU;STA
set-up time for a repeated START
condition
4.7 - 0.6 - s
t
HD;STA
hold time (repeated) START condition 4 - 0.6 - s
t
SU;STO
set-up time for STOP condition 4 - 0.6 - s
t
VD;DAT
data valid time SCL LOW to
SDA output valid
-3.45 - 0.9s
t
VD;ACK
data valid acknowledge time ACK signal
from SCL LOW
to SDA (out) LOW
-3.45 - 0.9s
Table 34. Switching characteristics
Over recommended operating free air temperature range; C
L
 100 pF; unless otherwise specified. See Figure 30.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
Unit
Min Max Min Max
t
v(INT)
valid time on pin INT from P port to INT -1-1s
t
rst(INT)
reset time on pin INT from SCL to INT -1-1s
t
v(Q)
data output valid time from SCL to P port - 400 - 400 ns
t
su(D)
data input set-up time from P port to SCL 0 - 0 - ns
t
h(D)
data input hold time from P port to SCL 300 - 300 - ns