Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 22 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
Reducing the current drive capability may be desirable to reduce system noise. When the
output switches (transitions from H/L), there is a peak current that is a function of the
output drive selection. This peak current runs through V
DD
and V
SS
package inductance
and will create noise (some radiated, but more critically Simultaneous Switching Noise
(SSN)). In other words, switching many outputs at the same time will create ground and
supply noise. The output drive strength control through the Current Control registers
allows the user to mitigate SSN issues without the need of additional external
components.
8.3 Power-on reset requirements
In the event of a glitch or data corruption, PCAL9535A can be reset to its default
conditions by using the power-on reset feature. Power-on reset requires that the device
go through a power cycle to be completely reset. This reset also happens when the device
is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17
and Figure 18.
Table 28 specifies the performance of the power-on reset feature for PCAL9535A for both
types of power-on reset.
Fig 17. V
DD
is lowered below 0.2 V or to 0 V and then ramped up to V
DD
Fig 18. V
DD
is lowered below the POR threshold, then ramped back up to V
DD
002aah329
V
DD
time
ramp-up ramp-down
(dV/dt)
r
(dV/dt)
f
re-ramp-up
(dV/dt)
r
time to re-ramp
when V
DD
drops
below 0.2 V or to V
SS
t
d(rst)
002aah330
V
DD
time
ramp-down
(dV/dt)
f
ramp-up
(dV/dt)
r
time to re-ramp
when V
DD
drops
to V
POR(min)
− 50 mV
t
d(rst)
V
I
drops below POR levels