Datasheet

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PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2 — 23 January 2015 18 of 46 NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Fig 11. Read input port register (non-latched), scenario 2
1 0 0 A2 A1 A0 1 AS0
START condition
R/W
acknowledge
from slave
002aah376
A
SCL
SDA A
read from port 0
P
987654321
I0.xslave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t
v(INT)
t
rst(INT)
DATA 00 DATA 10 DATA 03 DATA 12
DATA 00 DATA 01
t
h(D)
t
h(D)
DATA 02
t
su(D)
DATA 03
t
su(D)
DATA 10 DATA 11 DATA 12