Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 16 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
7.2 Reading the port registers
In order to read data from the PCAL9535A, the bus master must first send the
PCAL9535A address with the least significant bit set to a logic 0 (see Figure 4
“PCAL9535A device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte is sent by the PCAL9535A (see Figure 9
, Figure 10 and
Figure 11
). Data is clocked into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be read but the data now reflects
the information in the other register in the pair. For example, if Input Port 1 is read, the
next byte read is Input Port 0. There is no limit on the number of data bytes received in
one read transmission, but on the final byte received the bus master must not
acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9. Read from register
AS
START condition R/W
acknowledge
from slave
002aah374
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
1 0 0 A2 A1 A00 0
data from lower or
upper byte of register
LSBMSB
DATA (last byte)
data from upper or
lower byte of register
LSBMSB
0/1 0 0 0/1 0/1 0/1 0/10
command byte