Datasheet

PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 2 — 23 January 2015 13 of 46
NXP Semiconductors
PCAL9535A
Low-voltage 16-bit I
2
C-bus I/O port with interrupt and Agile I/O
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
DD
or V
SS
. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
6.4 Power-on reset
When power (from 0 V) is applied to V
DD
, an internal power-on reset holds the
PCAL9535A in a reset condition until V
DD
has reached V
POR
. At that time, the reset
condition is released and the PCAL9535A registers and I
2
C-bus/SMBus state machine
initializes to their default states. After that, V
DD
must be lowered to below V
PORF
and back
up to the operating voltage for a power-reset cycle. See Section 8.3 “
Power-on reset
requirements”.
At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
INTERRUPT
MASK
V
DD
P0_0 to P0_7
P1_0 to P1_7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
002aah428
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
V
DD
ESD
protection
diode
input port
latch
DQ
EN
LATCH
read pulse
input latch
register
DQ
CK
FF
data from
shift register
write input
latch pulse