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1. General description

The PCAL9535A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander

with interrupt and reset for I

C-bus/SMBus applications. NXP I/O expanders provide a

simple solution when additional I/Os are needed while keeping interconnections to a

minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control,

etc.

In addition to providing a flexible set of GPIOs, the wide V

range of 1.65 V to 5.5 V

allows the PCAL9535A to interface with next-generation microprocessors and

microcontrollers where supply levels are dropping down to conserve power.

The PCAL9535A contains the PCA9535 register set of four pairs of 8-bit Configuration,

Input, Output, and Polarity Inversion registers, and additionally, the PCAL9535A has

Agile I/O, which are additional features specifically designed to enhance the I/O. These

additional features are: programmable output drive strength, latchable inputs,

programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,

programmable open-drain or push-pull outputs.

The PCAL9535A is a pin-to-pin replacement to the PCA9535 and PCA9535A, however,

the PCAL9535A powers up with all I/O interrupts masked. This mask default allows for a

board bring-up free of spurious interrupts at power-up.

The PCAL9535A open-drain interrupt (INT

) output is activated when any input state differs

from its corresponding Input Port register state and is used to indicate to the system

master that an input state has changed.

INT

can be connected to the interrupt input of a microcontroller. By sending an interrupt

signal on this line, the remote I/O can inform the microcontroller if there is incoming data

on its ports without having to communicate via the I

C-bus. Thus, the PCAL9535A can

remain a simple slave device.

The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming

low device current.

The power-on reset sets the registers to their default values and initializes the device state

machine.

Three hardware pins (A0, A1, A2) select the fixed I

C-bus address and allow up to eight

devices to share the same I

C-bus/SMBus.

PCAL9535A

Low-voltage 16-bit I

C-bus I/O port with interrupt and Agile I/O

Rev. 2 — 23 January 2015 Product data sheet

Summary of content (46 pages)

PAGE 1
PCAL9535A Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Rev. 2 — 23 January 2015 Product data sheet 1. General description The PCAL9535A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander with interrupt and reset for I2C-bus/SMBus applications. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control, etc.
PAGE 2
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 2. Features and benefits  I2C-bus to parallel port expander  Operating power supply voltage range of 1.65 V to 5.5 V  Low standby current consumption:  1.5 A (typical at 5 V VDD)  1.0 A (typical at 3.3 V VDD)  Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs  Vhys = 0.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 3. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCAL9535AHF L35A HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4  4  0.75 mm SOT994-1 PCAL9535APW PCAL9535A TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 3.1 Ordering options Table 2.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 5. Pinning information 5.1 Pinning 19 SCL terminal 1 index area 21 VDD 20 SDA 2 22 INT A1 24 VDD 23 SDA 24 A2 1 23 A1 PCAL9535AHF INT 6 19 P1_6 P0_2 3 16 P1_6 P0_3 7 18 P1_5 P0_3 4 15 P1_5 P0_4 8 17 P1_4 P0_4 5 14 P1_4 P0_5 9 16 P1_3 P0_5 6 13 P1_3 P0_6 10 15 P1_2 P0_7 11 14 P1_1 VSS 12 13 P1_0 PCAL9535APW 002aah427 Transparent top view 002aah426 Fig 2.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Table 3. Pin description …continued Symbol Pin Type Description 17 I/O Port 1 input/output 7. 21 18 I Address input 0. Connect directly to VDD or VSS. SCL 22 19 I Serial clock bus. Connect to VDD through a pull-up resistor. SDA 23 20 I/O Serial data bus. Connect to VDD through a pull-up resistor. VDD 24 21 power Supply voltage.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O B7 B6 B5 B4 B3 B2 B1 B0 002aaf540 Fig 5. Table 4.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.2.2 Input port register pair (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. The default value ‘X’ is determined by the externally applied logic level.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.2.4 Polarity inversion register pair (04h, 05h) The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the Input register.
PAGE 9
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is controlled by register 41 CC0.6(bits [5:4]).
PAGE 10
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ‘1’. The next read of the input port 0 register bit 4 register should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.2.9 Pull-up/pull-down selection register pair (48h, 49h) The I/O port can be configured to have a pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin.
PAGE 12
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.2.11 Interrupt status register pair (4Ch, 4Dh) These read-only registers are used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD or VSS.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 6.5 Interrupt output An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back to the original value or when data is read form the port that generated the interrupt (see Figure 10).
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 2 3 4 5 6 7 8 9 slave address SDA S 0 1 0 data to port 0 command byte 0 A2 A1 A0 0 START con
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 7.2 Reading the port registers In order to read data from the PCAL9535A, the bus master must first send the PCAL9535A address with the least significant bit set to a logic 0 (see Figure 4 “PCAL9535A device address”). The command byte is sent after the address and determines which register will be accessed.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCAL9535A Product data sheet data into port 0 data into port 1 tv(INT) SCL 1 2 3
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DATA 00 DATA 01 DATA 02 DATA 03 tsu(D) th(D) data into port 1 NXP Semiconductors PCAL9535A Product
PAGE 19
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DATA 01 DATA 02 NXP Semiconductors PCAL9535A Product data sheet data into port 0 DATA 01 tsu(D) data
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 8. Application design-in information VDD (3.3 V) 10 kΩ 10 kΩ 10 kΩ 2 kΩ VDD VDD MASTER CONTROLLER PCAL9535A SUB-SYSTEM 1(1) (e.g., temp sensor) 100 kΩ (×3) INT SCL SCL P0_0 SDA SDA P0_1 INT INT SUB-SYSTEM 2 (e.g., counter) P0_2 RESET P0_3 VSS A P0_4 controlled switch (e.g., CBT device) enable P0_5 B P0_6 P0_7 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 A2 A1 A0 SUB-SYSTEM 3(1) (e.g.
PAGE 21
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 3.3 V VDD VDD LED 5V VDD 100 kΩ LED Pn Pn 002aag164 Fig 14. High value resistor in parallel with the LED 002aag165 Fig 15. Device supplied by a lower voltage 8.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels.
PAGE 22
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)).
PAGE 23
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Table 28. Recommended supply sequencing and ramp rates Tamb = 25 C (unless otherwise noted). Not tested; specified by design. Symbol Parameter Condition Min Typ Max Unit (dV/dt)f fall rate of change of voltage Figure 17 0.1 - 2000 ms (dV/dt)r rise rate of change of voltage Figure 17 0.1 - 2000 ms td(rst) reset delay time Figure 17; re-ramp time when VDD drops below 0.
PAGE 24
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 8.4 Device current consumption with internal pull-up and pull-down resistors The PCAL9535A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails.
PAGE 25
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 9. Limiting values Table 29. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Min Max Unit 0.5 +6.5 V 0.5 +6.5 V 0.5 +6.
PAGE 26
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 12. Static characteristics Table 32. Static characteristics Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage II = 18 mA 1.2 - - V VPOR power-on reset voltage VI = VDD or VSS; IO = 0 mA - 1.1 1.4 V VOH HIGH-level output voltage[2] P port; IOH = 8 mA; CCX.X = 11b VDD = 1.65 V 1.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Table 32. Static characteristics …continued Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified. Min Typ[1] Max Unit VDD = 3.6 V to 5.5 V - 10 25 A VDD = 2.3 V to 3.6 V - 6.5 15 A VDD = 1.65 V to 2.3 V - 4 9 A VDD = 3.6 V to 5.5 V - 1.5 7 A VDD = 2.3 V to 3.6 V - 1 3.2 A VDD = 1.65 V to 2.3 V - 0.5 1.7 A VDD = 3.6 V to 5.5 V - 60 125 A VDD = 2.
PAGE 28
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 12.1 Typical characteristics 002aah333 20 IDD (μA) 16 12 002aah334 1400 IDD(stb) (nA) VDD = 5.5 V 5.0 V 3.6 V 3.3 V 2.5 V 2.3 V VDD = 5.5 V 5.0 V 3.6 V 3.3 V 1000 800 600 8 400 2.5 V 2.3 V 1.8 V 1.65 V 4 0 −40 200 VDD = 1.8 V 1.65 V −15 10 35 0 −40 60 85 Tamb (°C) Fig 21. Supply current versus ambient temperature 002aah335 20 IDD (μA) 16 −15 10 35 60 85 Tamb (°C) Fig 22.
PAGE 29
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Isink (mA) 002aaf578 35 Isink (mA) 30 Tamb = −40 °C 25 °C 85 °C 25 002aaf579 35 30 Tamb = −40 °C 25 °C 85 °C 25 20 20 15 15 10 10 5 5 0 0 0 0.1 0.2 0.3 0 0.1 0.2 VOL (V) a. VDD = 1.65 V Isink (mA) b. VDD = 1.8 V 002aaf580 50 002aaf581 60 Isink (mA) 40 Tamb = −40 °C 25 °C 85 °C 30 0.3 VOL (V) Tamb = −40 °C 25 °C 85 °C 40 20 20 10 0 0 0 0.1 0.2 0.3 0 0.1 0.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 002aah110 30 Isource (mA) Isource (mA) Tamb = −40 °C 25 °C 85 °C 20 002aah111 35 Tamb = −40 °C 25 °C 85 °C 30 25 20 15 10 10 5 0 0 0 0.2 0.4 0.6 VDD − VOH (V) a. VDD = 1.65 V 0 002aah112 Isource (mA) Tamb = −40 °C 25 °C 85 °C 40 0.4 0.6 VDD − VOH (V) b. VDD = 1.8 V 60 Isource (mA) 0.2 002aah113 70 Tamb = −40 °C 25 °C 85 °C 60 50 40 30 20 20 10 0 0 0 0.2 0.4 0.6 VDD − VOH (V) c.
PAGE 31
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O VOL (mV) 002aah056 120 100 002aah343 200 VDD − VOH (mV) 160 (1) 80 120 VDD = 1.8 V 5V 60 (2) 80 40 (4) 20 0 −40 40 (3) −15 10 35 60 85 Tamb (°C) 0 −40 −15 10 35 60 85 Tamb (°C) Isource = 10 mA (1) VDD = 1.8 V; Isink = 10 mA (2) VDD = 5 V; Isink = 10 mA (3) VDD = 1.8 V; Isink = 1 mA (4) VDD = 5 V; Isink = 1 mA Fig 27.
PAGE 32
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 13. Dynamic characteristics Table 33. I2C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 29. Conditions Standard-mode Fast-mode I2C-bus Unit I2C-bus Symbol Parameter Min Max Min Max fSCL SCL clock frequency 0 100 0 400 tHIGH HIGH period of the SCL clock 4 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.
PAGE 33
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 14. Parameter measurement information VDD RL = 1 kΩ DUT SDA CL = 50 pF 002aag803 a. SDA load configuration two bytes for read Input port register(1) STOP START condition condition (P) (S) Address Bit 7 (MSB) Address Bit 1 R/W Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Data Bit 0 (LSB) STOP condition (P) 002aag952 b. Transaction format tHIGH tLOW tSP 0.7 × VDD 0.
PAGE 34
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O VDD RL = 4.7 kΩ INT DUT CL = 100 pF 002aah069 a.
PAGE 35
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 500 Ω Pn DUT 2 × VDD CL = 50 pF 500 Ω 002aag805 a. P port load configuration SCL P0 A P7 0.7 × VDD 0.3 × VDD SDA tv(Q) Pn unstable data last stable bit A P7 002aag806 b. Write mode (R/W = 0) SCL P0 0.7 × VDD 0.3 × VDD tsu(D) th(D) Pn 002aag807 c. Read mode (R/W = 1) CL includes probe and jig capacitance. tv(Q) is measured from 0.7  VDD on SCL to 50 % I/O (Pn) output.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 15. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.
PAGE 37
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm B D SOT994-1 A terminal 1 index area E A A1 c detail X e1 1/2 e ∅v ∅w b e 7 12 M M C C A B C y1 C y L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.
PAGE 38
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 34. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
PAGE 41
PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP24 package SOT355-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 8.200 5.300 8.600 7.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Footprint information for reflow soldering of HVQFN24 package SOT994-1 Hx Gx D P 0.025 0.025 C (0.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 19. Abbreviations Table 37.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
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PCAL9535A NXP Semiconductors Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 23. Contents 1 2 2.1 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . .