Datasheet

Product data sheet Rev. 6 — 9 October 2014 9 of 61

NXP Semiconductors

PCAL6416A

Low-voltage translating 16-bit I

C-bus/SMBus I/O expander

7. Functional description

Refer to Figure 1 “Block diagram of PCAL6416A (positive logic)”.

7.1 Device address

The address of the PCAL6416A is shown in Figure 9.

ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW

(logic 0) to assign one of the two possible slave addresses. The last bit of the slave

address (R/W

) defines the operation (read or write) to be performed. A HIGH (logic 1)

selects a read operation, while a LOW (logic 0) selects a write operation.

7.2 Interface definition

7.3 Pointer register and command byte

Following the successful acknowledgement of the address byte, the bus master sends a

command byte, which is stored in the Pointer register in the PCAL6416A. The lower three

bits of this data byte state the operation (read or write) and the internal registers (Input,

Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with

the lower three bits of the Command byte are used to point to the extended features of the

device (Agile IO). This register is write only.

Fig 9. PCAL6416A address

R/W

002aah045

0 1 0 0 0 0

fixed

slave address

hardware selectable

Table 5. Interface definition

Byte Bit

7 (MSB) 6 5 4 3 2 1 0 (LSB)

C-bus slave address L H L L L L ADDR R/W

I/O data bus P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Fig 10. Pointer register bits

002aaf540

B7 B6 B5 B4 B3 B2 B1 B0