Datasheet

PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 7 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
5.2 Pin description
[1] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input.
[2] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input.
Table 3. Pin description
Symbol Pin Description
TSSOP24 HWQFN24 VFBGA24 UFBGA24,
XFBGA24
INT
1 22 A3 B3 Interrupt output. Connect to V
DD(I2C-bus)
or V
DD(P)
through a pull-up resistor.
V
DD(I2C-bus)
2 23 B3 A2 Supply voltage of I
2
C-bus. Connect directly to the V
DD
of the external I
2
C master. Provides voltage-level
translation.
RESET
3 24 A2 A1 Active LOW reset input. Connect to V
DD(I2C-bus)
through a pull-up resistor if no active connection is
used.
P0_0
[1]
4 1 A1 B1 Port 0 input/output 0.
P0_1
[1]
5 2 C3 C3 Port 0 input/output 1.
P0_2
[1]
6 3 B1 C1 Port 0 input/output 2.
P0_3
[1]
7 4 C1 C2 Port 0 input/output 3.
P0_4
[1]
8 5 C2 D1 Port 0 input/output 4.
P0_5
[1]
9 6 D1 E1 Port 0 input/output 5.
P0_6
[1]
10 7 E1 E2 Port 0 input/output 6.
P0_7
[1]
11 8 D2 D2 Port 0 input/output 7.
V
SS
12 9 E2 E3 Ground.
P1_0
[2]
13 10 E3 D3 Port 1 input/output 0.
P1_1
[2]
14 11 E4 E4 Port 1 input/output 1.
P1_2
[2]
15 12 D3 E5 Port 1 input/output 2.
P1_3
[2]
16 13 E5 D5 Port 1 input/output 3.
P1_4
[2]
17 14 D4 D4 Port 1 input/output 4.
P1_5
[2]
18 15 D5 C5 Port 1 input/output 5.
P1_6
[2]
19 16 C5 C4 Port 1 input/output 6.
P1_7
[2]
20 17 C4 B5 Port 1 input/output 7.
ADDR 21 18 B5 A5 Address input. Connect directly to V
DD(P)
or ground.
SCL 22 19 A5 A4 Serial clock bus. Connect to V
DD(I2C-bus)
through a
pull-up resistor.
SDA 23 20 A4 B4 Serial data bus. Connect to V
DD(I2C-bus)
through a
pull-up resistor.
V
DD(P)
24 21 B4 A3 Supply voltage of PCAL6416A for Port P.