Datasheet
PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 5 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
5. Pinning information
5.1 Pinning
The exposed center pad, if used, must be
connected only as a secondary ground or
must be left electrically open.
Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24
An empty cell indicates no ball
is populated at that grid point.
Fig 4. Pin configuration for VFBGA24
(3 mm 3 mm)
Fig 5. Ball mapping for 3 mm 3 mm
VFBGA24 (transparent top view)
PCAL6416APW
INT V
DD(P)
V
DD(I2C-bus)
SDA
RESET SCL
P0_0 ADDR
P0_1 P1_7
P0_2 P1_6
P0_3 P1_5
P0_4 P1_4
P0_5 P1_3
P0_6 P1_2
P0_7 P1_1
V
SS
P1_0
002aaf963
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aaf964
Transparent top view
P1_3
P0_4
P0_5
P1_4
P0_3 P1_5
P0_2 P1_6
P0_1 P1_7
P0_0 ADDR
P0_6
P0_7
V
SS
P1_0
P1_1
P1_2
RESET
V
DD(I2C-bus)
INT
V
DD(P)
SDA
SCL
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
PCAL6416AHF
002aaf966
PCAL6416AEV
Transparent top view
D
B
E
C
A
ball A1
index area
12345
P0_0 RESET SDA SCL
12345
P0_2 V
DD(I2C-bus)
V
DD(P)
ADDR
A
B
P0_3 P0_4 P0_1 P1_7 P1_6C
P0_5 P1_2 P1_4 P1_5D
P0_6 V
SS
P1_0 P1_1 P1_3E
P0_7
002aag244
INT