Datasheet

PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 17 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
7.6 Power-on reset
When power (from 0 V) is applied to V
DD(P)
, an internal power-on reset holds the
PCAL6416A in a reset condition until V
DD(P)
has reached V
POR
. At that time, the reset
condition is released and the PCAL6416A registers and I
2
C-bus/SMBus state machine
initializes to their default states. After that, V
DD(P)
must be lowered to below V
POR
and
back up to the operating voltage for a power-reset cycle. See Section 9.3 “
Power-on reset
requirements”.
7.7 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the V
DD(P)
at its
operating level. A reset can be accomplished by holding the RESET
pin LOW for a
minimum of t
w(rst)
. The PCAL6416A registers and I
2
C-bus/SMBus state machine are
changed to their default state once RESET
is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to V
DD(I2C-bus)
if no active connection is used.
On power-up or reset, all registers return to default values.
Fig 11. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
INTERRUPT
MASK
V
DD(P)
P0_0 to P0_7
P1_0 to P1_7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
002aag971
FF
data from
shift register
FF
FF
FF
Q1
Q2
V
SS
to INT
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
V
DD(P)
ESD
protection
diode
input port
latch
DQ
EN
LATCH
read pulse
input latch
register
DQ
CK
FF
data from
shift register
write input
latch pulse