Datasheet

PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 16 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
7.4.10 Interrupt status register pair (4Ch, 4Dh)
These read-only registers are used to identify the source of an interrupt. When read, a
logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write operation is described in Section 8.1
. A
register pair read operation is described in Section 8.2
.
7.4.11 Output port configuration register (4Fh)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 11
). A logic 1
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence is to program this register (4Fh) before the configuration register
(06h and 07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
DD(P)
to a maximum of
5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
DD(P)
or V
SS
. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
Table 27. Interrupt status port 0 register (address 4Ch) bit description
Bit 7 6 5 4 3 2 1 0
Symbol S0.7 S0.6 S0.5 S0.4 S0.3 S0.2 S0.1 S0.0
Default 00000000
Table 28. Interrupt status port 1 register (address 4Dh) bit description
Bit 7 6 5 4 3 2 1 0
Symbol S1.7 S1.6 S1.5 S1.4 S1.3 S1.2 S1.1 S1.0
Default 00000000
Table 29. Output port configuration register (address 4Fh)
Bit 7 6 5 4 3 2 1 0
Symbol reserved ODEN1 ODEN0
Default 00000000