Datasheet

PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 9 October 2014 13 of 61
NXP Semiconductors
PCAL6416A
Low-voltage translating 16-bit I
2
C-bus/SMBus I/O expander
7.4.5 Output drive strength register pairs (40h, 41h, 42h, 43h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO
can be configured independently to a certain output current level by two register control
bits. For example Port 0.7 is controlled by register 41 CC0.7 (bits [7:6]), Port 0.6 is
controlled by register 41 CC0.6 (bits [5:4]). The output drive level of the GPIO is
programmed 00b = 0.25, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of
the I/O. See Section 9.2 “
Output drive strength control” for more details. A register pair
write operation is described in Section 8.1
. A register pair read operation is described in
Section 8.2
.
7.4.6 Input latch register pair (44h, 45h)
The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O
pins. These registers are effective only when the pin is configured as an input port. When
an input latch register bit is 0, the corresponding input pin state is not latched. A state
change in the corresponding input pin generates an interrupt. A read of the input register
clears the interrupt. If the input goes back to its initial logic state before the input port
register is read, then the interrupt is cleared.
When an input latch register bit is 1, the corresponding input pin state is latched. A change
of state of the input generates an interrupt and the input logic value is loaded into the
corresponding bit of the input port register (registers 0 and 1). A read of the input port
register clears the interrupt. If the input pin returns to its initial logic state before the input
port register is read, then the interrupt is not cleared and the corresponding bit of the input
port register keeps the logic value that initiated the interrupt. See Figure 17
.
For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to
logic 0, the input port 0 register will capture this change and an interrupt is generated (if
unmasked). When the read is performed on the input port 0 register, the interrupt is
Table 15. Current control port 0 register (address 40h)
Bit 7 6 5 4 3 2 1 0
Symbol CC0.3 CC0.2 CC0.1 CC0.0
Default 11111111
Table 16. Current control port 0 register (address 41h)
Bit 7 6 5 4 3 2 1 0
Symbol CC0.7 CC0.6 CC0.5 CC0.4
Default 11111111
Table 17. Current control port 1 register (address 42h)
Bit 7 6 5 4 3 2 1 0
Symbol CC1.3 CC1.2 CC1.1 CC1.0
Default 11111111
Table 18. Current control port 1 register (address 43h)
Bit 7 6 5 4 3 2 1 0
Symbol CC1.7 CC1.6 CC1.5 CC1.4
Default 11111111